1. Technical Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, relates to a semiconductor device that can reduce an area occupied by an alignment mark such as a scribe line formed in an alignment area and a method of manufacturing the same.
2. Description of the Related Art
A semiconductor device having a multilayer wiring structure is formed by means of stacking a plurality of insulation layers or wiring layers using a photolithography, but an alignment mark is used in positioning the patterns transferred by the photolithography with respect to each layer. The alignment marks have various shapes according to the exposing system, but, generally, are formed by means of arranging marks having angle of several xcexcm in several to several tens of matrix shapes. The positioning of a semiconductor substrate is performed by means of exposing the alignment mark to a laser beam and detecting the reflected right thereof. Then, after a layer is formed, wiring and through holes are formed by means of performing process such as etching to the layer using a resist pattern to which a mask pattern is transferred.
In this case, a method of manufacturing a semiconductor device using the conventional alignment mark will be discussed with reference to FIGS. 1A through 1G (first prior art). FIGS. 1A through 1G are cross sectional views schematically and sequentially showing a forming method of an alignment mark in the manufacturing processes of the semiconductor device according to the first prior art, and illustrate cross sections of an alignment area such as a scribe line. Also, this prior art shows only an alignment area, and does not show a circuit pattern area where transistor and the like are formed.
First, predetermined transistor, etc. are formed (not shown) in a circuit pattern area of a semiconductor substrate such as Si (not shown). Next, as shown in FIG. 1A, a first insulation layer 1 comprised of a silicon oxide film, etc. is formed, and then, after a metal layer of Al, etc. is deposited, a resist layer is formed, and then, an alignment is performed by using a mark (not shown) previously formed on the semiconductor substrate which becomes a base as a reference, after that, the resist layer is exposed. And, process such as a dry etching is carried out by using a resist pattern formed by the exposure as a mask, so that a first wiring layer is formed in the circuit pattern area, and at the same time, an alignment mark 2a comprised of the same metal layer as the first wiring layer is formed in the alignment area such as the scribe line. Further, the alignment mark explained in the prior art is comprised of about several tens of rows with three columns of marks arranged at predetermined intervals, and the cross section of a line direction will be explained.
Next, after a second insulation layer 3 is deposited on the first wiring layer, a resist layer is formed, and an exposure is carried out by means of using the alignment mark 2a as a reference. And, a dry etching process is performed by using a resist pattern formed by the exposure as a mask, so that first through holes are formed in the circuit pattern area, and at the same time, an alignment mark 3a in which the first through holes are arranged is formed in the alignment area.
In addition, the first through holes are formed on the first wiring layer in the circuit pattern area which is not shown, but because the first wiring layer is not formed under the second insulation layer 3 in the alignment area shown in FIG. 1A, the thickness of the second insulation layer 3 is thicker than that of the circuit pattern area. In this case, since the condition of the dry etching to form the through holes are set according to the thickness of the insulation layer in the circuit pattern area, the first through holes in the alignment area do not penetrate the second insulation layer 3, and have a shape that the etching is stopped in the middle portion of the second insulation layer 3.
Next, as shown FIG. 1B, after a metal layer such as Al is deposited on the second insulation layer 3, a predetermined resist layer (not shown) is formed, and then, a resist pattern (not shown) is formed by performing an alignment by using the alignment mark 3a depositing the metal layer as a reference. A dry etching process is performed by means of using the resist pattern as a mask, so that a second wiring layer 4 is formed in the circuit pattern area. In addition, as shown in FIG. 1C, an alignment mark 4a is formed in the alignment area.
Next, as shown in FIG. 1D, after a third insulation layer 5 is deposited on the second wiring layer 4, a predetermined resist layer (not shown) is formed, and then, an exposure is performed by using the alignment mark 4a formed of the second wiring layer 4 as a reference, so that a resist pattern (not shown) having a predetermined opening is formed. After that, a dry etching is performed by means of using the resist pattern as a mask, so that second through holes penetrating the third insulation layer 5 are formed in the circuit pattern area, and at the same time, an alignment mark 5a in which the second through holes are arranged is formed in the alignment area.
Next, as shown in FIG. 1E, after a metal layer such as Al is deposited on the third insulation layer 5, a predetermined resist layer is formed, and then, an alignment is performed by using the alignment mark 5a depositing the metal layer as a reference, so that a resist pattern (not shown) is formed. A dry etching process is performed by using the resist pattern as a mask, so that a third wiring layer 6 is formed in the circuit pattern area, and at the same time, as shown in FIG. 1F, an alignment mark 6a is formed in the alignment area. After that, a semiconductor device as shown in FIG. 1G in which a plurality of wiring layers (seven layers in this prior art) are stacked is manufactured by repeating the same processes sequentially.
As such, conventionally, when forming the patterns of each wiring layer 4, 6, an alignment is performed by using the alignment marks 3a, 5a comprised of the through holes of the insulation layers 3, 5 just under the wiring layers 4, 6, and alignment marks 4a, 6a comprised of a wiring metal are newly formed on the alignment area such as a scribe line, on the other hand, when forming the through holes in each insulation layer 3, 5, an alignment is performed by using the alignment marks 2a, 4a comprised of the wiring layers 2, 4 just under the insulation layers, and the alignment marks 3a, 5a comprised of the through holes are formed on the alignment area.
That is, in case of alternately stacking wiring layers and insulation layers, since new alignment marks are formed according to the formation of the wiring layers and the through holes in the insulation layers, the alignment marks having the same number as the sum of the deposited wiring layers and insulation layers are formed in a new place in the alignment area. In detail, in case where seven wiring layers are formed as shown in the present prior art, total fourteen alignment marks including the insulation layers are formed.
However, in the recent semiconductor devices having a multilayer wiring structure, because the number of alignment marks are increased by making in a multilayer form, and at the same time, more accurate alignment is demanded by minuteness, the arranged number of the marks constituting alignment mark are increased, and an area occupied by one alignment mark becomes great. On the other hand, since a shape of the alignment mark are determined by the used exposing system, the shape thereof cannot be changed freely, and the area occupied by the alignment mark in the alignment area such as a scribe line as a whole semiconductor device becomes great, and thus, there is a problem that other accessory or check pattern for confirming the operation of the semiconductor device cannot be inserted into the scribe line.
As a method of solving the problem, the official gazettes of Japanese Patent Laid-Open No. hei 9-232207, etc. describe the method of arranging the alignment marks formed in each insulation layer or metal layer such that they are overlapped with each other in a normal direction to a semiconductor substrate. The method will be explained below with reference to FIGS. 2A through 2G and FIG. 3. FIGS. 2A through 2G and FIG. 3 are improvement of the first prior art, are cross sectional views sequentially showing the second prior art to reduce an area occupied by an alignment mark, and illustrate only an alignment area similarly to the above-mentioned first prior art.
First, in the same manner as the above-mentioned first prior art, after predetermined transistor, etc. are formed on a semiconductor substrate (not shown) such as Si, as shown in FIG. 2A, a first insulation layer 1 comprised of a silicon oxide layer, etc. and a metal layer of Al, etc. are deposited. Next, a predetermined resist layer (not shown) is formed, and an exposure is performed by means of using a mark (not shown) previously formed on a predetermined position of the semiconductor substrate as a reference, so that a resist pattern is formed. And, a dry etching is performed by means of using the resist pattern as a mask, so that a first wiring layer is formed in a circuit pattern area, and at the same time, an alignment mark 2a in which the metal layer is arranged in a matrix shape is formed in a first area of an alignment area.
Next, after a second insulation layer 3 is deposited on the first wiring layer, a resist predetermined layer (not shown) is formed, and then, an exposure is performed by means of using the first alignment mark 2a as a reference. And, a dry etching is performed by using a resist pattern (not shown) formed by the exposure as a mask, so that first through holes penetrating the second insulation layer 3 are formed in the circuit pattern area, and at the same time, an alignment mark 3a in which the first through holes are arranged in a matrix shape is formed in a second area of the alignment area. In addition, the reason why the alignment mark 3a does not penetrate the second insulation layer 3 and etching is stopped in the middle portion of the second insulation layer 3 is the same as that of the above-mentioned first prior art.
Next, as shown in FIGS. 2B and 2C, after a metal layer is deposited on the second insulation layer 3, a predetermined resist layer (not shown) is formed, and then, a resist pattern (not shown) is formed by performing an alignment by means of using the alignment mark 3a comprised of the first through holes formed in the previous process as a reference. And, a dry etching process is performed by using the resist pattern as a mask, however, in the second prior art, an alignment mark 4a comprised of the second wiring layer 4 is formed in a third area of the scribe line, and at the same time, a light-shielding layer 4d is formed in the upper part of the alignment mark 2a in the first area.
Next, as shown in FIG. 2D, after a third insulation layer 5 is deposited on the second wiring layer 4, a predetermined resist layer (not shown) is formed, and then, an exposure is performed by using the alignment mark 4a as a reference, so that a resist pattern (not shown) having an opening is formed on the light-shielding layer 4d. After that, a dry etching is performed by means of using the resist pattern as a mask, so that second through holes penetrating the third insulation layer 5 are formed in the circuit pattern area, and an alignment mark 5a reaching the light-shielding layer 4d is formed in the first area of the alignment area.
Next, as shown in FIG. 2E and FIG. 2F, after a metal layer such as Al is deposited on the third insulation layer 5, a predetermined resist layer (not shown) is formed, and then, an alignment performed by using the alignment mark 5a comprised of the second through holes formed in the previous process as a reference, so that a resist pattern (not shown) is formed. And, a dry etching process is performed by using the resist pattern as a mask, so that an alignment mark 6a comprised of the third wiring layer 6 is formed in a fourth area of the alignment area, and at the same time, a light-shielding layer 6d is formed in the upper part of the alignment mark 4a in the third area.
Next, as shown in FIG. 2G, after a fourth insulation layer 7 is deposited on the third wiring layer 6, a predetermined resist layer (not shown) is formed, and then, an exposure is performed by using the alignment mark 6a in the fourth area as a reference, so that a resist pattern (not shown) having an opening is formed on the light-shielding layer 6d. After that, a dry etching is performed by means of using the resist pattern as a mask, so that an alignment mark 7a comprised of third through holes reaching the light-shielding layer 6d is formed in the third area where the light-shielding layer 6d is formed. After that, a semiconductor device shown in FIG. 3 can be manufactured by repeating the above-mentioned processes of FIGS. 2A through 2G.
In the method described in the above-mentioned second prior art, since other alignment marks 5a, 7a, 15a composed of the through holes via the light-shielding layers 4d, 6d, 14d are formed in the upper layer of the alignment marks 2a, 4a, 12a comprised of the wiring layer, a ratio occupied by the alignment mark can be reduced, but since it is necessary that the light-shielding layers are formed so as to cover the whole alignment marks and an alignment mark is formed by arranging severalxc3x97several tens of marks, a large number of light-shielding layers having large area, concretely, a large number of light-shielding layers comprised of a metal layer having a size of about several tens of xcexcmxc3x97several hundreds of xcexcm are arranged in the alignment area.
An object of the present invention is to provide a semiconductor device that can reduce an area occupied by the alignment mark of a scribe line without separately providing a metal layer having a large size such as a light-shielding layer and a method of manufacturing the same.
According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a multilayer wiring structure in which wiring layers and insulation layers are alternately stacked are formed, and an alignment of each layer is performed by using an alignment mark provided in a predetermined alignment area. Said method comprises the steps of: performing the alignment of said wiring layer with respect to said insulation layer by using an alignment mark formed of a plurality of through holes provided in said insulation layer just under said wiring layer, when forming said wiring layer; and performing the alignment of said insulation layer with respect to said wiring layer by using an alignment mark provided in the lowermost wiring layer, when forming the through holes in each of said insulation layers.
According to the present invention, it is preferred to form an underlay having a larger shape than that of said through holes, at the same step of forming said wiring layer, at a position which is aligned to each through hole of said alignment mark which should be formed in said insulation layer just above said wiring layer.
Also, when forming said wiring layer, an etching of said wiring layer may be performed so as to form a convex portion extended outwardly from an inner wall of said through hole on an upper edge of each through hole of said alignment mark formed in said insulation layer just under said wiring layer.
Further, according to the present invention, there may be provided the constitution that said alignment marks formed in each of said insulation layers are sequentially formed in two or three areas within said predetermined alignment area, and said alignment marks in each area are arranged so as to be overlapped with each other as seen in a normal direction to the substrate.
According to another aspect of the present invention, there is provided a semiconductor device having a multilayer wiring structure in which wiring layers and insulation layers are alternately stacked, and an alignment of each layer is performed by using an alignment mark provided in a predetermined alignment area. Said semiconductor device comprises: alignment marks having through holes provided in said insulation layers, to be used in the alignment of said wiring layers with respect to said insulation layers; and an alignment mark provided in the lowermost wiring layer, to be used in the alignment of all of said insulation layers.
According to the present invention, it is preferred that an underlay is formed, at the same step of forming said wiring layer just under said insulation layer, in the lower part of each through hole of said alignment mark formed in each of said insulation layers. A shape of said underlay is larger than that of said through holes as seen in a normal direction to the substrate.
Also, a convex portion may be provided formed of the wiring layer just above said insulation layer and extended outwardly from an upper edge of said through hole of said alignment mark formed in each of said insulation layers.
Further, according to the present invention, said alignment marks formed in each of said insulation layers may be sequentially formed in two or three areas within said predetermined alignment area, and said alignment marks in each area may be arranged so as to be overlapped with each other as seen in a normal direction to the substrate.
According to the present invention, since through holes are formed in all the insulation layers deposited above the first wiring layer and in a polyimide layer which is an uppermost layer to be used as a protection layer of a semiconductor device by using an alignment mark which is formed with the first wiring layer, and alignment marks formed of the through holes are overlapped with each other, and the alignment marks are not formed in a new area when forming the through holes in the insulation layer, the area occupied by the alignment marks can be reduced, thereby, the chip size can be effectively utilized.
Further, according to the present invention, a saucer which becomes a underlay is formed in the lower area of the through holes, and an alignment mark is formed by means of penetrating the through holes up to the saucer, so that an uniformity of an alignment mark shape in a wafer surface can be improved, thereby, the effect that the pattern of the wiring layer on the through holes can be precisely formed is exhibited.
In addition, according to the present invention, since it is unnecessary to provide a light-shielding layer for preventing the light reflected from the alignment mark of the lower layer, occurrence of metal film pieces causing short in providing the semiconductor device can be prevented.